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| DSP56F802/D Rev. 0, 1/2002 DSP56F802 Preliminary Technical Data DSP56F802 16-bit Digital Signal Processor * * * Up to 40 MIPS operation at 80 MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 8K x 16-bit words Program Flash 1K x 16-bit words Program RAM 2K x 16-bit words Data Flash 1K x 16-bit words Data RAM 2K x 16-bit words Boot Flash * * * * * * * * * Hardware DO and REP loops 6-channel PWM Module with fault input Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel) Serial Communications Interface (SCI) Two General Purpose Quad Timers with 2 external outputs JTAG/OnCETM port for debugging 4 shared GPIO On-chip relaxation oscillator 32-pin LQFP Package * * * * * 6 PWM Outputs Fault A0 PWMA RESET 5 JTAG/ OnCE Port VCAPC VDD 2 2 3 Digital Reg Analog Reg VSS* VDDA VSSA 2 3 A/D1 A/D2 VREF ADC Interrupt Controller Low Voltage Supervisor Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit Quad Timer C Quad Timer D or GPIO Program Memory 8188 x 16 Flash 1024 x 16 SRAM Boot Flash 2048x 16 Flash Data Memory 2048 x 16 Flash 1024 x 16 SRAM * PAB * * PDB * * * * IPBB CONTROLS 16 Relaxation Oscillator PLL 2 XDB2 CGDB XAB1 XAB2 . * 2 SCI0 or GPIO INTERRUPT CONTROLS 16 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] 16-Bit DSP56800 Core ApplicationSpecific Memory & Peripherals IPBus Bridge (IPBB) *includes TCS pin which is reserved for factory use and is tied to VSS Figure 1. DSP56F802 Block Diagram (c) Motorola, Inc., 2002. All rights reserved. Part 1 Overview 1.1 DSP56F802 Features 1.1.1 * * * * * * * * * * * * * * Digital Signal Processing Core Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface 1.1.2 * * Memory Harvard architecture permits as many as three simultaneous accesses to program and data memory On-chip memory including a low-cost, high-volume flash solution -- 8K x 16 bit words of Program Flash -- 1K x 16-bit words of Program RAM -- 2K x 16-bit words of Data Flash -- 1K x 16-bit words of Data RAM -- 2K x 16-bit words of Boot Flash * Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces (JTAG) 1.1.3 * * * * * Peripheral Circuits for DSP56F802 Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection; supports both center- and edge-aligned modes Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support two simultaneous conversions; ADC and PWM modules can be synchronized Two General Purpose Quad Timers with two external pins (or two GPIO) Serial Communication Interface (SCI) with two pins (or two GPIO) Four multiplexed General Purpose I/O (GPIO) pins 2 DSP56F802 Preliminary Technical Data MOTOROLA DSP56F802 Description * * * * * * Computer-Operating Properly (COP) watchdog timer External interrupts via GPIO Trimmable on-chip relaxation oscillator External reset pin for hardware reset JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock 1.1.4 * * * * * Energy Information Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available Integrated power supervisor 1.2 DSP56F802 Description The DSP56F802 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the DSP56F802 is well-suited for many applications. The DSP56F802 includes many peripherals that are especially useful for applications such as motion control, home appliances, encoders, tachometers, limit switches, power supply and control, engine management, and industrial control for power, lighting, automation and HVAC. The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The DSP56F802 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The DSP56F802 also provides and up to 4 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The DSP56F802 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 1K words of both program and data RAM. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main program and data flash memory areas. Both program and data flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the DSP56F802 is the inclusion of a Pulse Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Both edge and center aligned synchronous pulse width control (0% to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC MOTOROLA DSP56F802 Preliminary Technical Data 3 Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection with sufficient output drive capability to directly drive standard opto-isolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. The PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital Converters. The DSP56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels. A full set of standard programmable peripherals is provided that include a Serial Communications Interface (SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator eliminates the need for an external crystal. 1.3 "Best in Class" Development Environment The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique C application code independent of component architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1 are required for a complete description and proper design with the DSP56F802. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp. Table 1. DSP56F802 Chip Documentation Topic DSP56800 Family Manual DSP56F801/803/805/807 User's Manual Description Detailed description of the DSP56800 family architecture, and 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56F801, DSP56F802, DSP56F803, DSP56F805, and DSP56F807 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the DSP56F802 core, memory, peripherals and interfaces Order Number DSP56800FM/D DSP56F801-7UM/D DSP56F802 Technical Data Sheet DSP56F802 Product Brief DSP56F802/D DSP56F802PB/D 4 DSP56F802 Preliminary Technical Data MOTOROLA Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN 1. Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL "asserted" "deasserted" Examples: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MOTOROLA DSP56F802 Preliminary Technical Data 5 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56F802 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 11, each table row describes the signal or signals present on a pin. Table 2. Functional Group Pin Allocations Functional Group Power (VDD or VDDA) Ground (VSS, VSSA, TCS) Supply Capacitors Program Control Pulse Width Modulator (PWM) Port and Fault Input Serial Communications Interface (SCI) Port1 Analog-to-Digital Converter (ADC) Port (including VREF) Quad Timer Module Port JTAG/On-Chip Emulation (OnCE) 1. Alternately, GPIO pins Number of Pins 3 4 2 1 7 2 6 2 5 Detailed Description Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 6 DSP56F802 Preliminary Technical Data MOTOROLA Introduction Power Port Ground Port Power Port Ground Port VDD VSS VDDA VSSA 2 3* 1 1 PWMA0-5 Other Supply Port VCAPC 6 2 1 Fault A0 DSP56F802 1 1 TXD0 (GPIOB0) RXD0 (GPIOB1) SCI0 Port or GPIO 5 1 TCK JTAG/ OnCETM Port TMS TDI TDO TRST ANA2-4, ANA6-7 VREF ADCA Port 1 1 2 1 1 1 TD1-2 (GPIOA1-2) Quad Timer D or GPIO 1 RESET Program Control Figure 2. DSP56F802 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. *includes TCS pin which is reserved for factory use and is tied to VSS MOTOROLA DSP56F802 Preliminary Technical Data 7 2.2 Power and Ground Signals Table 3. Power Inputs No. of Pins 2 Signal Name VDD Signal Description Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. Analog Power--This pin supplies an analog power source. 1 VDDA Table 4. Grounds No. of Pins 2 Signal Name VSS Signal Description GND--These pins provide grounding for the internal structures of the chip, and should all be attached to VSS. Analog Ground--This pin supplies an analog ground. TCS--This pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional V SS. 1 1 VSSA TCS Table 5. Supply Capacitors and VPP No. of Pins 2 Signal Name VCAPC Signal Type Supply State During Reset Supply Signal Description VCAPC - Connect each pin to a 2.2 F bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, refer to Section 5.2 2.3 Interrupt and Program Control Signals Table 6. Program Control Signals No. of Pins 1 Signal Name RESET Signal Type Input State During Reset Input Signal Description Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. 8 DSP56F802 Preliminary Technical Data MOTOROLA Pulse Width Modulator (PWM) Signals 2.4 Pulse Width Modulator (PWM) Signals Table 7. Pulse Width Modulator (PWMA) Signals No. of Pins 6 1 Signal Name PWMA0-5 FAULTA0 Signal Type Output Input State During Reset Tri-stated Input Signal Description PWMA0-5-- These are six PWMA output pins. FAULTA0 --This fault input is used for disabling selected PWMA outputs in cases where fault conditions originate off chip. 2.5 Serial Communications Interface (SCI) Signals Table 8. Serial Communications Interface (SCI0) Signals No. of Pins 1 Signal Name TXD0 GPIOB0 Signal Type Output Input/ Output State During Reset Input Input Signal Description Transmit Data (TXD0)--transmit data output Port B GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. 1 RXD0 GPIOB1 Input Input/ Output Input Input Receive Data (RXD0)--receive data input Port B GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 2.6 Analog-to-Digital Converter (ADC) Signals Table 9. Analog to Digital Converter Signals No. of Pins 3 2 1 Signal Name ANA2-4 ANA6-7 VREF Signal Type Input Input Input State During Reset Input Input Input Signal Description ANA2-4--Analog inputs to ADC channel 1 ANA6-7--Analog inputs to ADC channel 2 VREF--Analog reference voltage. Must be set to VDDA - 0.3V = 3.0V for optimal performance. MOTOROLA DSP56F802 Preliminary Technical Data 9 2.7 Quad Timer Module Signals Table 10. Quad Timer Module Signals No. of Pins 2 Signal Name TD1-2 Signal Type Input/ Output Input/ Output State During Reset Input Signal Description TD1-2--Timer D Channel 1-2 GPIOA1-2 Input Port A GPIO--These pins are General Purpose I/O (GPIO) pins that can individually be programmed as input or output pins. After reset, the default state is the quad timer input. 2.8 JTAG/OnCE Table 11. JTAG/On-Chip Emulation (OnCE) Signals No. of Pins 1 Signal Name TCK Signal Type Input State During Reset Signal Description Input, pulled Test Clock Input--This input pin provides a gated clock to low internally synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. Input, pulled Test Mode Select Input--This input pin is used to sequence the JTAG high internally TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Input, pulled Test Data Input--This input pin provides a serial input data stream to high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Tri-stated Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. 1 TMS Input 1 TDI Input 1 TDO Output 1 TRST Input Input, pulled Test Reset--As an input, a low signal on this pin provides a reset high internally signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the OnCE/JTAG module on the DSP. 10 DSP56F802 Preliminary Technical Data MOTOROLA General Characteristics Part 3 Specifications 3.1 General Characteristics The DSP56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5Vcompatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56F802 DC and AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 12. Absolute Maximum Ratings Characteristic Supply voltage All other input voltages, excluding Analog inputs Analog Inputs ANAx, VREF Current drain per pin excluding VDD, VSS, & PWM ouputs Current drain per pin for PWM outputs Junction temperature Storage temperature range Symbol VDD VIN VIN I I TJ TSTG Min VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -55 Max VSS + 4.0 VSS + 5.5V VDDA + 0.3V 10 20 150 150 Unit V V V mA mA C C MOTOROLA DSP56F802 Preliminary Technical Data 11 Table 13. Recommended Operating Conditions Characteristic Supply voltage Ambient operating temperature Symbol VDD TA Min 3.0 -40 Max 3.6 85 Unit V C Table 14. Thermal Characteristics 1 32-pin LQFP Characteristic Symbol Junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed PD 1. See Section 5.1 for more detail. RJA PI/O PD PDMAX Value 53.2 User Determined PD = (IDD x VDD) + PI/O (TJ - TA) / JA Unit C/W W W C 3.2 DC Electrical Characteristics Table 15. DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Characteristic Input high voltage Input low voltage Input current low (pullups/pulldowns disabled) Input current high (pullups/pulldowns disabled) Typical pullup or pulldown resistance Input/output tri-state current low Input/output tri-state current low Output High Voltage (at IOH) Output Low Voltage (at IOL) Output High Current Output Low Current Input capacitance Output capacitance Symbol VIH VIL IIL IIH RPU, RPD IOZL IOZH VOH VOL IOH IOL CIN COUT Min 2.0 -0.3 -1 -1 -- -10 -10 VDD - 0.7 -- -- -- -- -- Typ -- -- -- -- 30 -- -- -- -- -- -- 8 12 Max 5.5 0.8 1 1 -- 10 10 -- 0.4 -4 4 -- -- Unit V V A A K A A V V mA mA pF pF 12 DSP56F802 Preliminary Technical Data MOTOROLA DC Electrical Characteristics Table 15. DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fop = 80 MHz Characteristic PWM pin output source current1 PWM pin output sink current2 VDD supply current Run4 Wait5 Stop Low Voltage Interrupt6 Core Voltage Interrupt Power on Reset7 VEI POR Symbol IOHP IOLP IDDT3 -- -- -- 2.4 -- -- 103 72 60 2.7 2.2 1.7 138 98 84 2.9 -- 2.0 mA mA mA V Min -- -- Typ -- -- Max -10 16 Unit mA mA V 1. PWM pin output source current measured with 50% duty cycle. 2. PWM pin output sink current measured with 50% duty cycle. 3. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 4. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 5. Wait IDD measured using internal relaxation oscillator set to 8 MHz; all inputs 0.2V from rail; no DC loads; less than 50 pF on all outputs. CL = 20 pF on EXTAL; all ports configured as inputs; measured with PLL enabled. 6. Low voltage interrupt monitors the VDD supply. When VDD drops below VEI value, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEI. 7. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below VPOR. While power is ramping up, this signal remains active for as long as the internal 2.5V supply is below 1.5V no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates. Digital (VDD=3.6V) Analog (VDDA=3.6V) Total 180 150 120 90 Idd (mA) 60 30 0 0 20 40 Freq. (MHz) 60 80 Figure 3. Maximum Run Idd vs. Frequency (see Note 4 above) MOTOROLA DSP56F802 Preliminary Technical Data 13 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins except XTAL, which is tested using the input levels in Section 3.2 In Figure 4 the levels of VIH and VIL for an input signal are shown. VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH - VIL)/2. Low High 90% 50% 10% VIL Rise Time Figure 4. Input Signal Measurement References Figure 5 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data Valid state, when a signal level has reached V OL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data3 Valid Data3 Data Active Figure 5. Signal States 14 DSP56F802 Preliminary Technical Data MOTOROLA Flash Memory Characteristics 3.4 Flash Memory Characteristics Table 16. Flash Memory Truth Table Mode Standby Read Word Program Page Erase Mass Erase 1. 2. 3. 4. 5. 6. 7. 8. XE1 L H H H H YE2 L H H L L SE3 L H L L L OE4 L H L L L PROG5 L L H L L ERASE6 L L L H H MAS17 L L L L H NVSTR8 L L H H H X address enable, all rows are disabled when XE = 0 Y address enable, YMUX is disabled when YE = 0 Sense amplifier enable Output enable, tri-state flash data out bus when OE = 0 Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle Table 17. IFREN Truth Table Mode Read Word program Page erase Mass erase IFREN = 1 Read information block Program information block Erase information block Erase both blocks IFREN = 0 Read main memory block Program main memory block Erase main memory block Erase main memory block MOTOROLA DSP56F802 Preliminary Technical Data 15 Table 18. Timing Symbols Characteristic PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time(mass erase) NVSTR to program set up time Program hold time Address/data set up time Address/data hold time Recovery time Cumulative program HV period Program time Erase time Mass erase time Symbol See Figure(s) Figure 6, Figure 7, Figure 8 Figure 6, Figure 7 Figure 8 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6, Figure 7, Figure 8 Figure 6 Figure 6 Figure 7 Figure 8 Tnvs Tnvh Tnvh1 Tpgs Tpgh Tads Tadh Trcv Thv Tprog Terase Tme Table 19. Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF Characteristic Program time Erase time Mass erase time Endurance1 Data Retention @ 5,000 Cycles1 Symbol Min 20 20 100 10,000 10 Typ -- -- -- 20,000 30 Max -- -- -- -- -- Unit us ms ms cycles years Tprog Terase Tme ECYC DRET The following parameters should only be used in the Manual Word Programming mode. PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time(mass erase) NVSTR to program set up time Recovery time 1. Tnvs Tnvh Tnvh1 Tpgs Trcv -- -- -- -- -- 5 5 100 10 1 -- -- -- -- -- us us us us us One cycle is equal to an erase, program, and read. 16 DSP56F802 Preliminary Technical Data MOTOROLA Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs NVSTR Tpgs Thv Tnvh Trcv Tprog Tpgh Figure 6. Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 7. Flash Erase Cycle MOTOROLA DSP56F802 Preliminary Technical Data 17 IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 8. Flash Mass Erase Cycle 3.5 Clock Operation The DSP56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a master reference frequency that determines the speed at which chip operations occur. The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal oscillator use. 3.5.1 Use of On-Chip Relaxation Oscillator The DSP56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10 show the typical characteristics of the DSP56F802 relaxation oscillator with respect to temperature and trim value. During factory production test, an oscillator calibration procedure is executed which determines an optimum trim value for a given device (8 MHz at 25 oC). This optimum trim value is then stored at address $103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence (executed after power-up and RESET). This trim routine automatically sets the oscillator frequency by programming the IOSCTL register with the optimum trim value. Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code must be included which retrieves the optimum trim value (from address $103F in the Data Flash Information Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control register must be set in order to read the Data Flash Information Block. MOTOROLA 18 DSP56F802 Preliminary Technical Data Clock Operation Table 20. Relaxation Oscillator Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Frequency Accuracy1 Frequency Drift over Temp Frequency Drift over Supply 1. Over full temperature range. Symbol f f/t f/V Min -- -- -- Typ +2 +0.1 0.1 Max +5 -- -- Unit % %/oC %/V 8.4 8.3 Output Frequency 8.2 8.1 8.0 7.9 7.8 -40 -25 -5 15 35 55 75 85 Temperature (oC) Figure 9. Typical Relaxation Oscillator Frequency vs. Temperature (Trimmed to 8 MHz @ 25oC) MOTOROLA DSP56F802 Preliminary Technical Data 19 11 10 9 8 7 6 5 0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 Figure 10. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC 3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 21. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 RESET De-assertion to First External Address Output Edge-sensitive Interrupt Request Width 1. 2. Symbol tRAZ tRA 275,000T 128T tRDA tIRW 33T 1.5T -- -- 34T -- ns ns ns ns Typical Min -- Typical Max 21 Unit ns In the formulas, T = clock cycle. For an operating frequency of 80 MHz, T = 12.5 ns. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state 20 DSP56F802 Preliminary Technical Data MOTOROLA Quad Timer Timing Figure 11. External Level-Sensitive Interrupt Timing General Purpose I/O Pin tIG IRQA b) General Purpose I/O 3.7 Quad Timer Timing Table 22. Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. 2. Symbol PIN PINHL POUT POUTHL Typical Min 4T+6 2T+3 2T 1T Typical Max -- -- -- -- Unit ns ns ns ns In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 12. Timer Timing MOTOROLA DSP56F802 Preliminary Technical Data 21 3.8 Serial Communication Interface (SCI) Timing Table 23. SCI Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width 1. 2. 3. 4. Symbol BR RXDPW TXDPW Min Max (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps ns ns -- 0.965/BR 0.965/BR fMAX is the frequency of operation of the system clock in MHz. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 13. RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 14. TXD Pulse Width 3.9 Analog-to-Digital Converter (ADC) Characteristics Table 24. ADC Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, ADC clock = 4MHz, 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Input voltages Resolution Integral Non-Linearity2 Differential Non-Linearity Monotonicity ADC internal clock Conversion range fADIC RAD 0.5 VSSA Symbol VADIN RES INL DNL Min 0 12 -- -- Typ -- -- +/- 4 +/- 0.9 GUARANTEED -- -- 5 VDDA MHz V Max VDDA1 12 +/- 5 +/- 1 Unit V Bits LSB3 LSB3 22 DSP56F802 Preliminary Technical Data MOTOROLA Analog-to-Digital Converter (ADC) Characteristics Table 24. ADC Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, ADC clock = 4MHz, 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic Power-up time Conversion time Sample time Input capacitance Gain Error (transfer gain) Offset Voltage Total Harmonic Distortion Signal-to-Noise plus Distortion Effective Number of Bits Spurious Free Dynamic Range Spurious Free Dynamic Range ADC Quiescent Current (both ADCs) VREF Quiescent Current (both ADCs) Symbol tADPU tADC tADS CADI EGAIN VOFFSET THD SINAD ENOB SFDR SFDR IADC IVREF Min -- -- -- -- 1.00 +10 55 54 8.5 60 65 -- -- Typ 2.5 6 1 5 1.10 +230 60 56 9.5 65 70 39.3 11.85 Max -- -- -- -- 1.15 +325 -- -- -- -- -- -- 14.5 Unit msec tAIC cycles4 tAIC cycles4 pF4 -- mV dB -- bit dB dB mA mA 1. VDDA should be tied to the same potential as VDD via separate traces. VREF must be equal to or less than VDD and must be greater than or equal to 2.7V. 2. 3. Measured in 10-90% range. LSB = Least Significant Bit. 4. tAIC = 1/fADIC ADC analog input 3 1 2 4 Figure 15. Equivalent Analog Input Circuit 1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. 2.04pf 3. Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. 1pf MOTOROLA DSP56F802 Preliminary Technical Data 23 3.10 JTAG Timing Table 25. JTAG Timing 1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50 pF, fOP = 80 MHz Characteristic TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time Symbol fOP tCY tPW tDS tDH tDV tTS tTRST Min DC 100 50 0.4 1.2 -- -- 50 Max 10 -- -- -- -- 26.6 23.5 -- Unit MHz ns ns ns ns ns ns ns 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW VIH tPW VM TCK (Input) VM = VIL + (VIH - VIL)/2 VM VIL Figure 16. Test Clock Input Timing Diagram 24 DSP56F802 Preliminary Technical Data MOTOROLA JTAG Timing TCK (Input) TDI TMS (Input) TDO (Output) tTS tDS tDH Input Data Valid tDV Output Data Valid TDO (Output) tDV TDO (Output) Output Data Valid Figure 17. Test Access Port Timing Diagram TRST (Input) tTRST Figure 18. TRST Timing Diagram MOTOROLA DSP56F802 Preliminary Technical Data 25 Part 4 Packaging 4.1 Package and Pin-Out Information DSP56F802 This section contains package and pin-out information for the 32-pin LQFP configuration of the DSP56F802. VCAPC1 PWMA3 PWMA2 PWMA1 PWMA0 ANA7 ANA6 PWMA4 PWMA5 ORIENTATION MARK 25 ANA4 ANA3 VREF PIN 1 TD1 TD2 TXDO VSS VDD 9 RXD0 Motorola DSP56F802 17 ANA2 FAULTA0 VSS VDD VSSA VDDA VCAPC2 Figure 19. Top View, DSP56F802 32-pin LQFP Package RESET TRST TDO TMS TCS TCK TDI 26 DSP56F802 Preliminary Technical Data MOTOROLA Package and Pin-Out Information DSP56F802 Table 26. DSP56F802 Pin Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 Signal Name PWMA4 PWMA5 TD1 TD2 TXDO VSS VDD RXD0 Pin No. 9 10 11 12 13 14 15 16 Signal Name TCS TCK TMS TDI VCAPC2 TDO TRST RESET Pin No. 17 18 19 20 21 22 23 24 Signal Name VDDA VSSA VDD VSS FAULTA0 ANA2 VREF ANA3 Pin No. 25 26 27 28 29 30 31 32 Signal Name ANA4 ANA6 ANA7 PWMA0 VCAPC1 PWMA1 PWMA2 PWMA3 MOTOROLA DSP56F802 Preliminary Technical Data 27 1. 2. 3. 4. 5. 6. 7. NOTES: DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE A, B AND D TO BE DETERMINED AT DATUM PLANE H. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. DIMENSIONS b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THEN 0.08 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTURSION: 0.07 MM. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 MM PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 O O1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.15 0.05 1.45 1.35 0.45 0.30 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 -0.20 REF Figure 20. 32-pin LQFP Mechanical Information (Case 873A) 28 DSP56F802 Preliminary Technical Data MOTOROLA Thermal Design Considerations Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: TJ = T A + ( PD x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. * * MOTOROLA DSP56F802 Preliminary Technical Data 29 The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition on page 45. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct DSP operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place six 0.01-0.1 F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be 150 milliohm or less ESR capacitors. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS. Bypass the VDD and VSS layers of the PCB with approximately 100 F, preferably with a highgrade capacitor such as a tantalum capacitor. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. DSP56F802 Preliminary Technical Data MOTOROLA * * * * * * 30 Electrical Design Considerations * Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. TRST must be asserted at power up for proper operation. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. * Part 6 Ordering Information Table 27 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 27. DSP56F802 Ordering Information Part DSP56F802 Supply Voltage 3.0-3.6 V Package Type Low Profile Plastic Quad Flat Pack (LQFP) Pin Count 32 Frequency (MHz) 80 Order Number DSP56F802TA80 MOTOROLA DSP56F802 Preliminary Technical Data 31 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/ DSP56F802/D |
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